`timescale 1ns / 1ps


module signal_gen_top
#(parameter T =20000 ,
  parameter sim = 0)
(
    input   wire            rst_n               ,
    input   wire            in_clk_50m          , 
    input   wire            f_adj               ,    
    input   wire            a_adj               ,
    input   wire            w_adj               ,
    input   wire            duty_adj            ,    
    input   wire            iq_adj              ,       
    input   wire            f_add_adj           ,    
    input   wire            f_sub_adj           ,          
    output                  dac_ch              ,
    output                  dac_clk             ,
    output                  dac_wr              ,
    output  [9:0]           dac_d               ,
    output                  led                 
    );

   assign  dac_clk =  dac_wr ;
    
    wire             stop            ;
    wire             sys_rst_n       ;
    wire             sys_clk_p       ;
    wire    [11 :0]  f_word          ;
    wire    [15:0]   p_word          ;
    wire    [7 :0]   rom_data        ;
    wire             add_en          ;
    
    pll_rst     pll_rst_inst(
        .clk_50m			( in_clk_50m		),
        .f_adj              ( f_adj             ),
        .stop               ( stop              ),
        .rst_n  			( ~rst_n      	    ),                       
        .sys_rst_n          ( sys_rst_n         ),
        .add_en             ( add_en            ),
        .sys_clk_p	        ( sys_clk_p	        ),
        .dac_clk_n	        ( dac_wr	        )
    
    );
     
    dds_module  
    # (.sim (sim))
    dds_module_inst(
        .add_en             ( add_en         ) ,
        .f_word             ( f_word         ) ,
        .p_word             ( p_word         ) ,
        .sys_clk_p          ( sys_clk_p      ) ,
        .sys_rst_n          ( sys_rst_n      ) , 
        .rom_data           ( rom_data       )
    
    );
    
    dds_ctrl  
    #(.T(T))
    dds_ctrl_inst(
        .sys_clk_p          ( sys_clk_p      )  ,
        .sys_rst_n          ( sys_rst_n      )  ,
        .duty_adj           ( duty_adj       ) ,
        .iq_adj             ( iq_adj         ) ,
        .a_adj              ( a_adj          ) ,
        .f_add_adj          ( f_add_adj      ) ,
        .f_sub_adj          ( f_sub_adj      ) ,                   
        .w_adj              ( w_adj          )  ,
        .rom_data           ( rom_data       )  ,             
        .f_word             ( f_word         )  ,
        .p_word             ( p_word         )  ,
        .mode               ( dac_ch         )  ,
        .led                ( led            )  ,
        .dac_out            ( dac_d          )
    );
       
endmodule    
    
    
    